In a conventional 2-bit-per-cycle SAR ADC, three capacitor arrays and three comparators are required to determine two bits in every cycle. However, because of the mismatch/offset between the capacitor arrays and the comparators, the calibrations are mandatory to prevent the performance degradation of the SAR ADC. The complexity and difficulty of the calibrations are related to the numbers of the capacitor arrays and the comparators, and the calibrations are easier if less capacitor arrays and the comparators are used. Therefore, how to provide a novel SAR ADC design with less capacitor arrays and the comparators is an important topic.